Silicon Labs /BGM220SC22WGA /RAC_NS /TX

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Interpret as TX

TX6DBMENREG=disable, TX0DBMENPREDRVREGBIAS=disable, TX6DBMENPREDRVREG=disable, TX6DBMENPACORE=disable, TX0DBMENBLEEDREG=disable, TX0DBMENPREDRVREG=disable, TX0DBMENBLEEDPREDRVREG=disable, TX0DBMENREG=disable, TX0DBMENRAMPCLK=disable, TX6DBMENPAOUT=disable, TX6DBMENRAMPCLK=disable_clock, TX6DBMENBLEEDREG=disable, TX6DBMENBLEEDPREDRVREG=disable, TX0DBMENBIAS=disable, TX0DBMENPREDRV=disable

Fields

TX0DBMENBLEEDPREDRVREG	TX0DBMENBLEEDPREDRVREG 0 (disable): undefined 1 (enable): undefined
TX0DBMENBLEEDREG	TX0DBMENBLEEDREG 0 (disable): undefined 1 (enable): undefined
TX0DBMENPREDRV	TX0DBMENPREDRV 0 (disable): undefined 1 (enable): undefined
TX0DBMENPREDRVREG	TX0DBMENPREDRVREG 0 (disable): undefined 1 (enable): undefined
TX0DBMENPREDRVREGBIAS	TX0DBMENPREDRVREGBIAS 0 (disable): undefined 1 (enable): undefined
TX0DBMENBIAS	TX0DBMENBIAS 0 (disable): undefined 1 (enable): undefined
TX0DBMENRAMPCLK	TX0DBMENRAMPCLK 0 (disable): undefined 1 (enable): undefined
TX0DBMENREG	TX0DBMENREG 0 (disable): undefined 1 (enable): undefined
TX6DBMENBLEEDPREDRVREG	TX6DBMENBLEEDPREDRVREG 0 (disable): undefined 1 (enable): undefined
TX6DBMENBLEEDREG	TX6DBMENBLEEDREG 0 (disable): undefined 1 (enable): undefined
TX6DBMENPREDRVREG	TX6DBMENPREDRVREG 0 (disable): undefined 1 (enable): undefined
TX6DBMENRAMPCLK	TX6DBMENRAMPCLK 0 (disable_clock): undefined 1 (enable_clock): undefined
TX6DBMENREG	TX6DBMENREG 0 (disable): undefined 1 (enable): undefined
TX6DBMENPACORE	TX6DBMENPACORE 0 (disable): undefined 1 (enable): undefined
TX6DBMENPAOUT	TX6DBMENPAOUT 0 (disable): undefined 1 (enable): undefined
ENXOSQBUFFILT	Override
ENPAPOWER	Override
ENPASELSLICE	Override

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